In recent years, a semiconductor integrated circuit which is designed to have a multilayer structure to pack semiconductor components at a higher density has been developed. In particular, a semiconductor circuit is conventionally formed on a semiconductor substrate of a single crystal. A coating of polycrystalline or substantially single-crystal semiconductor is formed on the semiconductor circuit. Another semiconductor circuit is formed on this coating. A typical example of this is a completely CMOS static RAM (SRAM) having two layers of MOS transistors. That is, MOS transistors are formed on a substrate of a single crystal. Thin-film transistors are formed over the MOS transistors. The conventional completely CMOS SRAM needs two pairs of CMOS transistors (i.e., two NMOS transistors and two PMOS transistors) and two driver NMOS transistors per storage cell. Hence, a large area is required. Therefore, these SRAM devices were supplanted by high-resistivity SRAM devices which use high-resistivity polysilicon instead of PMOS devices. The high-resistivity polysilicon forms plural layers as viewed from the transistors to increase the device density. However, where the device density increases greatly, the leakage current is too large when linear resistive devices are used as loads. For this reason, the conventional completely CMOS devices in which PMOS devices are used as loads have begun to be employed again, the PMOS devices being linear devices. However, the device density makes it impossible to adopt the prior art planar structure. At present, therefore, PMOS transistors are formed as thin-film transistors so as to create a multilayer structure.
This multilayer structure yields various advantages as well as the increased device density. In particular, one further advantage is that it is easy to separate devices. Especially, latchup which presents problems in the case of conventional CMOS monolithic integrated circuits does not take place. More specifically, in the multilayer structure described above, PMOS devices are completely separated from the substrate and from NMOS devices and so there is no possibility of the occurrence of parasitic transistors via NMOS devices adjacent to the substrate. Consequently, there is no probability that latchup occurs.
For these reasons, multilayer integrated circuits which are also known as three-dimensional ICs have been manufactured. However, the conventional multilayer ICs are fabricated by the same manufacturing steps as used to form conventional integrated circuits on a semiconductor substrate. Therefore, many masks are needed for the fabrication. For example, in order to built a CMOS inverter circuit from a multilayer integrated circuit having three layers of polysilicon and one layer of aluminum metallization interconnections, the following steps are necessitated after the first layer of MOS transistors having polysilicon gates using the first polysilicon layer is formed:
(1) Formation of a first interlayer insulator. PA1 (2) Formation and etching of a second polysilicon layer. This step needs a first mask. PA1 (3) Formation of a gate-insulating film. PA1 (4) Formation of holes in the interlayer insulator for connection with the gate interconnects of the first MOS transistors. This step needs a second mask. PA1 (5) Formation of the gate electrodes (a third layer of polysilicon) of second transistors. This step needs a third mask. PA1 (6) Implantation of dopant ions. PA1 (7) Formation of a second interlayer insulator. PA1 (8) Formation of holes in the second interlayer insulator to have access to source and drain electrodes. This step needs a fourth mask. PA1 (9) Formation of holes in the first interlayer insulator to have access to the source and drain electrodes. This step needs a fifth mask. PA1 (10) Formation of source and drain electrode interconnects. This step needs a sixth mask. PA1 (11) Formation of a passivation film. PA1 (1a) Formation of an interlayer insulator. PA1 (2a) Formation and etching of a second polysilicon layer. This step needs a first mask. PA1 (3a) Formation of a gate-insulating film. PA1 (4a) Formation of holes in the interlayer insulator for connection with the gate interconnects of the first MOS transistors. This step needs a second mask. PA1 (5a) Formation of the gate electrodes (a first aluminum layer) of second transistors. This step needs a third mask. PA1 (6a) Anodic oxidation of the surfaces of the gate electrodes and of the gate interconnects. PA1 (7a) Implantation of dopant ions. PA1 (8a) Removal of the gate-insulating film and exposing of the doped regions of the PMOS transistors. PA1 (9a) Formation of holes in the interlayer insulator to have access to the source and drain electrodes. This step needs a fourth mask. PA1 (10a) Formation of source and drain electrodes and interconnects, using the second aluminum layer. This step needs a fifth mask. PA1 (11a) Formation of a passivation film. PA1 (1b) Formation of an interlayer insulator. PA1 (2b) Formation and etching of a second polysilicon layer. This step needs a first mask. PA1 (3b) Formation of a gate-insulating film. PA1 (4b) Formation of the gate electrodes of second transistors (a first aluminum layer). This step needs a second mask. PA1 (5b) Anodic oxidation of the surfaces of the gate electrodes and of the gate interconnects. PA1 (6b) Implantation of dopant ions. PA1 (7b) Removal of the gate-insulating film and exposing of the doped regions of the PMOS transistors. PA1 (8b) Formation of holes in the interlayer insulator to have access to the source and drain electrodes. This step needs a third mask. PA1 (9b) Formation of source and drain electrodes and interconnects, using the second aluminum layer. This step needs a fourth mask. PA1 (10b) Formation of a passivation film. PA1 (1c) Formation of a first interlayer insulator. PA1 (2c) Formation and etching of a second polysilicon layer. This step needs a first mask. PA1 (3c) Formation of a gate-insulating film. PA1 (4c) Formation of holes in the interlayer insulator which are used for connection with the gate interconnects for first MOS transistors. This step needs a second mask. PA1 (5c) Formation of the gate electrodes of second transistors (a first aluminum layer). This step needs a third mask. PA1 (6c) Anodic oxidation of the surfaces of the gate electrodes and of the gate interconnects. PA1 (7c) Implantation of dopant ions. PA1 (8c) Formation of a second interlayer insulator. PA1 (9c) Formation of holes in the second interlayer insulator to have access to the source and drain electrodes. This step needs a fourth mask. PA1 (10c) Formation of holes in the second interlayer insulator to have access to the source and drain electrodes. This step needs a fifth mask. PA1 (11c) Formation of source and drain electrodes and interconnects, using the second aluminum layer. This step needs a sixth mask. PA1 (12c) Formation of a passivation film.
In this way, at least 6 masks are necessary. To increase the value of the integrated circuit, more masks are needed. Especially, in the steps (7) and (8) described above, if a CMOS inverter is fabricated, conductive interconnects connected with grounded portions must be formed independent of conductive interconnects for supplying drain voltages and, therefore, the use of a mask is unavoidable. In a CMOS transfer gate circuit, the doped regions of the NMOS and PMOS transistors are coupled. In this case, therefore, the doped region of the NMOS transistor overlaps the doped region of the PMOS transistor. Therefore, one might consider that it is not necessary to carry out two separate steps only if these two doped regions of the NMOS and PMOS transistors are connected with each other. Indeed, one would reasonably consider that if holes extending through the sources or drains of the NMOS or PMOS transistors are formed by the use of one mask, then contact to both MOS transistors can be made.
Researches made recently have revealed that decreasing the thickness of the doped region of a PMOS transistor improves the characteristics. Usually, the thickness is set less than 100 nm. Sometimes, doped regions as thin as 20 nm are utilized. Therefore, if only a hole extending through both doped regions is formed, the contact made is far from satisfaction. Typically, the radius of the hole is 2 .mu.m, and the thickness of the doped regions of the PMOS transistors is 100 nm. In this case, the total area of the electrodes formed in the NMOS transistor is about 12.6 .mu.m.sup.2, while the total area of the electrodes formed on the doped regions of the PMOS transistors is only one tenth of that area, i.e., 1.3 .mu.m.sup.2. This electrode area is too small, though the electric power consumed by the CMOS transistor is small. This small area cannot withstand normal operation.
Accordingly, a hole is formed in the second interlayer insulator, although this step is cumbersome to perform. Also, holes are formed to permit formation of electrodes connected with the doped region of the PMOS transistor. Then, holes extending through the second and first interlayer insulators are formed to permit formation of electrodes connected to the doped region of the NMOS transistor. The areas of the two kinds of electrode portions are made substantially equal.
Where the thickness of the doped region of the PMOS transistor is quite thin, e.g., less than 50 nm, sufficient care must be taken in forming a hole in the second interlayer insulator. Generally, the thickness of an interlayer insulator is made larger than 200 nm, taking account of the insulating characteristics of the insulator and the parasitic capacitance between the overlying and underlying conductive interconnection layers. In practice, the previously formed gate oxide film remains. This gate oxide film is 50 to 200 nm thick for thin-film transistors. Therefore, an oxide 250-400 nm or more thick exists on the doped region in practice.
Plasma etching is exploited for the formation of such a hole in the interlayer insulator. Although the ratio of the etch selectivity for silicon to the etch selectivity for silicon oxide is sufficiently large, the hole may erroneously extend into the silicon film unless the plasma etching process is carried out accurately. It is relatively easy to form holes in flat portions, but it is difficult to form holes in curved surfaces. Since the thickness of the interlayer insulator varies from location to location, it is quite difficult to terminate the etching at the surface of the silicon film over the whole length of the hole.
Obviously, a reduction in the number of masking steps is essential to increase in the production yield in manufacturing semiconductor integrated circuits and to reduce the cost.